homework 59

Answer the 10 questions.

1. A computer system using big endian stores a number as four bytes in standard IEEE floating point format as shown below in hex:

Address	Data
1237	0xC2
1236	0xAE
1235	0x40
1234	0x00

2. A) What is register renaming?

B) Give an example of assembly code where register renaming could be used to eliminate a dependency.

3. Use pseudo assembly code to give an example of the following:

A) A procedural dependency.

B) A true data dependency

C) An Output dependency

4.For a 16-bit word find the largest and smallest integer that can be represented by each of the following.Put your answers as decimal numbers.

A) Unsigned

B) Sign-magnitude

C) ones complement

D) twos complement

E) unsigned packed decimal

5. Justify the assertion that a 32-bit instruction is less than twice as useful as a 16-bit instruction.

6. A computer system using big endian stores a number as four bytes in standard IEEE floating point format as shown below in hex:

Address	Data
1237	0xC2
1236	0xAE
1235	0x40
1234	0x00

What is the number base 10.

7. A RISC machine has just two instruction formats as shown below.Answer the following questions:

A) What is the number of registers this machine can support?

B) How many different instructions are possible?

C) If the immediate field holds a twos complement number what is the range of immediate values?

D) How much memory could be accessed using this format?

8. The ARM Cortex M4 processor supports immediate operands but only in a very limited range.If you want to load a 32-bit operand into a register you can write the assembly instruction like this:

ldr R4, =0x12345678;

When the assembler sees this code it stores the immediate operand in code memory and sets up a relative load.For example

ldr R4, [PC, 10];Relative operand at PC + 10

At address PC + 10 it adds

DCW0x1234

DCW 0x5678

Why is this done?Why does the assembler change a 4 byte immediate operand to a relative address and store the 4 bytes in memory as a constant?

9. A non-pipelined computer has been built and, because they can overlap some of the opcode and operand decoding with the instruction execution, they find that they can clock the CPU at 62.5 MHz (every 16 nsec).

To speed things up the construct a pipelined version of the machine using a three-stage IED pipe.The time it takes to get through each stage is shown in the figure.

A) What is the fastest rate at which we can clock the pipelined machine in MHz.

B) How long, in the worst case, will it take a single instruction to get through the pipelined machine (in nsec)?

10. The program below executes on a RISC machine with a load and store architecture.Rewrite the code for a CISC machine that allows any register addressing mode to be used on source and destination operands for any instruction.Your goal is to reduce the number or instructions as much as possible.

LD r1, (r2);r1 ← Memory at r2 LD r3, (r4);r3 ← Memory at r4 LD r5, (r6);r5 ← Memory at r6 LD r7, (r8);r7 ← Memory at r8 DIV r9, r1, r3;r9 ← r1/r3 ADD r10, r9, r5;r10 ← r9 + r5 SUB r11, r7, r10;r11 ← r7 – r10 ST (r12), r11;Memory at r12 ← r11

 

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